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1 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom august 2000 ?2000 fairchild semiconductor international fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all speci- fications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout require- ments. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more informa- tion.) fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption. block diagram features extended operating voltage 2.7v ?5.5v 400 khz clock frequency (f) at 2.7v - 5.5v 200 a active current typical 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) iic compatible interface ?provides bi-directional data transfer protocol sixteen byte page write mode ?minimizes total write time per byte self timed write cycle typical write cycle time of 6ms hardware write protect for upper half (fm24c09u only) endurance: 1,000,000 data changes data retention greater than 40 years packages available: 8-pin dip, 8-pin so, and 8-pin tssop available in three temperature ranges - commercial: 0 to +70 c - extended (e): -40 to +85c - automotive (v): -40 to +125 c h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out a2
2 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom nc nc a2 v ss v cc nc scl sda 8 7 6 5 1 2 3 4 24c08 connection diagrams dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a2 device address input v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), so package (m8) and tssop package (mt8) see package number n08e, m08a and mtc08 pin names a2 device address input v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc no connection nc nc a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 24c09 note: pins designated as "nc" are typically unbonded pins. however some of them are bonded for special testing purposes. hence if a s ignal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the v cc applied to the device. this will ensure proper operation.
3 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom ordering information fm 24 c xx u f lz e xxx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range blank 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz process u ultralite cs100ul density 08 8k 09 8k with write protect c cmos technology interface 24 iic fm fairchild non-volatile memory
4 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 0.3v to 6.5v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature fm24c08u/09u 0 c to +70 c fm24c08ue/09ue -40 c to +85 c fm24c08uv/09uv -40 c to +125 c positive power supply fm24c08u/09u 4.5v to 5.5v fm24c08ul/09ul 2.7v to 5.5v fm24c08ulz/09ulz 2.7v to 5.5v dc electrical characteristics (2.7v to 5.5v) symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz ("f" version) 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 5.5v 10 50 a (note 3) or v cc v cc = 2.7v - 5.5v (l) 1 10 a v cc = 2.7v - 4.5v (lz) 0.1 1 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage of 5v for 4.5v-5.5v operation and at 3v for 2.7v-4.5v operation. note 2: this parameter is periodically sampled and not 100% tested. note 3: the "l" and "lz" versions can be operated in the 2.7v to 5.5v v cc range. however, for a standby current (i sb ) of 1 a, the v cc should be within 2.7v to 4.5v.
5 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf bus timing scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto 0.9v cc 0.1v cc 0.7v cc 0.3v cc read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time (note 4) 4.5v to 5.5v v cc 10 10 ms 2.7v to 4.5v v cc 15 15 note 4 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the fm24c08u/09u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address. refer "write cycle timing" diagram. ac testing input/output waveforms
6 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc sda scl 24c02/03 v cc v cc a0 a1 a2 v ss 24c02/03 a0 a1 a2 v ss 24c04/05 a1 a2 v ss 24c08/09 a2 v ss v cc to v ss to v ss to v ss v cc v cc v cc to v cc to v ss to v ss to v cc to v ss to v cc typical system configuration note: due to open drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf device address pins present memory size # of page a0 a1 a2 blocks fm24c02u/03u yes yes yes 2048 bits 1 fm24c04u/05u no yes yes 4096 bits 2 fm24c08u/09u no no yes 8192 bits 4 fm24c16u/17u no no no 16,384 bits 8 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
7 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom background information (iic bus) iic bus allows synchronous bi-directional communication be- tween a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally there are up to three address signals (a2, a1 and a0) which collectively serve as "chip select signal" to a device (example eeprom) on the iic bus. all communication on the iic bus must be started with a valid start condition (by a master), followed by transmittal (by the master) of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communication unless the receiver intends to discontinue the communication. depending on the direction of transfer (write or read), the re- ceiver can be a slave or the master. a typical iic communi- cation concludes with a stop condition (by the master). addressing an eeprom memory location involves sending a command string with the following information: [device type] [device/page block selection] [r/w bit] {acknowledge pulse} [array address] slave address slave address is an 8-bit information consisting of a device type field (4bits), device/page block selection field (3bits) and read/ write bit (1bit). slave address format acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. the receiver provides an ack pulse for every 8-bits of data received. this handshake mechanism is done as follows: after transmitting 8-bits of data, the transmitter re- leases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the 9th clock and releases the sda line back (to the transmitter). refer figure 3 . array address array address is an 8-bit information containing the address of a memory location to be selected within a page block of the device. 16k bit addressing limitation: standard iic specification limits the maximum size of eeprom memory on the bus to 16k bits. this limitation is due to the addressing protocol implemented which consists of the 8-bit slave address and an additional 8-bit field called array address. this array address selects 1 out of 256 locations (2 8 =256). since the data format of iic specification is 8-bit wide, a total of 256 x 8 = 2048 = 2k bits now becomes addressable by this 8-bit array address. these 2k bits are typically referred as a page block . combining this 8-bit array address with the 3-bit device/page address (part of slave address) allows a maximum of 8 pages (2 3 =8) of memory that can be addressed. since each page is 2k bits in size, 8 x 2k bit = 16k bits is the maximum size of memory that is addressable on the standard iic bus. this 16kb of memory can be in the form of a single 16kb eeprom device or multiple eeproms of varying density (in 2kb multiples) to a maximum total of 16kb. to address the needs of systems that require more than 16kb on the iic bus, a different specification called ex- tended iic specification is used. definitions word 8 bits (byte) of data page 16 sequential byte locations starting at a 16-byte address boundary, that may be pro- grammed during a "page write" programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) device type identifier device/page block selection 1 0 1 0 a2 a1 a0 r/w (lsb) device type iic bus is designed to support a variety of devices such as rams, eproms etc., along with eeproms. hence to properly identify various devices on the iic bus, a 4-bit device type identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own device type string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g. multiple eeproms) are present on the iic bus, then the a2, a1 and a0 address information bits are also used as part of the slave address. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a2, a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the device type comparison. in addition to selecting an eeprom, these 3 bits are also used to select a page block within the selected eeprom. each page block is 2kbit (256bytes) in size. depend- ing on the density, an eeprom can contain from a minimum of 1 to a maximum of 8 page blocks (in multiples of 2) and selection of a page block within a device is by using a2, a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is "1," then the access is read, whereas if the bit is "0," then the access is write.
8 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom eeprom number of device selection inputs address bits density page blocks provided selecting page block 2k bit 1 a0 a1 a2 none 4k bit 2 a1 a2 a0 8k bit 4 a2 a0 and a1 16k bit 8 a0, a1 and a2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. write protect (wp) (fm24c09u only) if tied to v cc , program operations onto the upper half (upper 4kbits) of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/ write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin is tied to v ss . device selection inputs a2, a1 and a0 (as appropriate) these inputs collectively serve as chip select signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs, if present, should be connected to v cc or v ss in a unique manner to allow proper selection of an eeprom amongst multiple eeproms. during a typical addressing se- quence, every eeprom on the iic bus compares the configura- tion of these inputs to the respective 3 bit device/page block selection information (part of slave address) to determine a valid selection. for e.g. if the 3 bit device/page block selection is 1- 0-1, then the eeprom whose device selection inputs (a2, a1 and a0) are connected to v cc -v ss -v cc respectively, is selected. depending on the density, only appropriate number of device selection inputs are provided on an eeprom. for every device selection input that is not present on the device, the correspond- ing bit in the device/page block selection field is used to select a page block within the device instead of the device itself. following table illustrates the above: note that even when just one eeprom present on the iic bus, these pins should be tied to v cc or v ss to ensure proper termina- tion. device operation the fm24c08u/09u supports a bi-directional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the fm24c08u/09u will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 1 and figure 2 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the fm24c08u/09u continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the fm24c08u/09u to place the device in the standby power mode, except when a write operation is being executed, in which case a second stop condition is required after t wr period, to place the device in standby mode.
9 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom data validity (figure 1) start and stop definition (figure 2) scl from master data output from transmitter data output from receiver 189 start condition acknowledge pulse t aa t dh sda scl start condition stop condition scl data stable data change sda acknowledge response from receiver (figure 3)
10 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom acknowledge the fm24c08u/09u device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the fm24c08u/09u will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the fm24c08u/09u slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected, fm24c08u/09u will continue to transmit data. if an acknowledge is not detected,fm24c08u/09u will terminate further data transmissions and await the stop condi- tion to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier. this is fixed as 1010 for all eeprom devices. refer the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses fm24c08u/09u p p a 4 00, 01, 10, 11 a: refers to a hardware configured device address pin. p: refers to an internal page block. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addresses 0x00 through 0xff). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte. the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the fm24c08u/09u recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the sda line low with an acknowledge signal and awaits further transmissions. device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) 24c08/09 page block address
11 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom write operations byte write for a write operation, a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address, the fm24c08u/09u responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition at which time the fm24c08u/ 09u begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress, the fm24c08u/09u inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer to figure 4 for the address, acknowledge, and data transfer sequence. page write to minimize write cycle time, fm24c08u/09u offer page write feature, by which, up to a maximum of 16 contiguous byte locations can be programmed all at once (instead of 16 individual byte writes). to facilitate this feature, the memory array is orga- nized in terms of pages. a page consists of 16 contiguous byte locations starting at every 16-byte address boundary (for ex- ample, starting at array address 0x00, 0x10, 0x20 etc.). page write operation limits access to byte locations within a page. in other words a single page write operation will not cross over to locations on another page but will roll over to the beginning of the page whenever end of page is reached and additional locations are continued to be accessed. a page write operation can be initiated to begin at any location within a page (starting address of the page write operation need not be the starting address of a page). s t o p bus activity: master sda line bus activity: eeprom data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: eeprom page write is initiated in the same manner as the byte write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 15 more bytes. after the receipt of each byte, fm24c08u/09u will respond with an acknowledge pulse, increment the internal address counter to the next address, and is ready to accept the next data. if the master should transmit more than sixteen bytes prior to generat- ing the stop condition, the address counter will roll over and previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 5 for the address, acknowledge, and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the host s write operation, the fm24c08u/09u initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the fm24c08u/09u is still busy with the write operation, no ack will be returned. if the fm24c08u/09u has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection (fm24c09u only) programming of the upper half (upper 4kbit) of the memory will not take place if the wp pin of the fm24c09u is connected to v cc . the fm24c09u will respond to slave and byte addresses; but if the memory accessed is write protected by the wp pin, the fm24c09u will not generate an acknowledge after the first byte of data has been received. thus the program cycle will not be started when the stop condition is asserted. byte write (figure 4) page write (figure 5)
12 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: eeprom data n s t o p a c k bus activity: master sda line bus activity: eeprom a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the fm24c08u/09u contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the fm24c08u/09u issues an acknowledge and transmits the eight bit word. the master will not acknowledge the transfer but does generate a stop condition, and therefore the fm24c08u/ 09u discontinues transmission. refer to figure 6 for the se- quence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address with the r/w bit set to zero and then the byte address is read. after the byte address acknowledge, the master immediately issues another start condition and the slave address with the r/w bit set to one. this will be followed by an acknowl- edge from the fm24c08u/09u and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the fm24c08u/09u discontinues transmission. refer to figure 7 for the address, acknowledge, and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the fm24c08u/09u continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. fm24c08u/09u continues to output data for each acknowledge received. refer to figure 8 for the address, acknowledge, and data transfer sequence. current address read (figure 6) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: eeprom 1 0 1 0 1 random read (figure 7) sequential read (figure 8)
13 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package (mt8) package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
14 www.fairchildsemi.com fm24c08u/09u rev. a.3 fm24c08u/09u C 8k-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
product folder - fairchild p/n fm24c09u - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c09u 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09u.html (1 of 3) [26-jul-2002 2:40:06 pm]
product folder - fairchild p/n fm24c09u - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c09uem8x full production $0.70 soic 8 $y&z&2&t 24u09 ue tape reel fm24c09um8 full production $0.66 soic 8 $y&z&2&t 24u09 m rail fm24c09un full production $0.67 dip 8 $y&z&2&t 24u09 n rail fm24c09um8x full production $0.66 soic 8 $y&z&2&t 24u09 m tape reel file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09u.html (2 of 3) [26-jul-2002 2:40:06 pm]
product folder - fairchild p/n fm24c09u - 8k-bit standard 2-wire bus interface serial eeprom fm24c09uem8 full production $0.70 soic 8 $y&z&2&t 24u09 ue rail * 1,000 piece budgetary pricing back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09u.html (3 of 3) [26-jul-2002 2:40:06 pm]
product folder - fairchild p/n fm24c08ufl - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c08ufl 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ufl.html (1 of 3) [26-jul-2002 2:40:26 pm]
product folder - fairchild p/n fm24c08ufl - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method FM24C08UFLEMT8X full production $0.70 tssop 8 &2&t $y2408 &z2408 fle rail fm24c08uflem8x full production $0.73 soic 8 $y&z&2&t 24u08 flem tape reel fm24c08uflm8x full production $0.70 soic 8 $y&z&2&t 24u08 flm tape reel fm24c08uflem8 full production $0.73 soic 8 $y&z&2&t 24u08 flem rail file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ufl.html (2 of 3) [26-jul-2002 2:40:26 pm]
product folder - fairchild p/n fm24c08ufl - 8k-bit standard 2-wire bus interface serial eeprom fm24c08uflemt8 full production $0.70 tssop 8 &2&t $y2408 &z2408 fle rail fm24c08uflm8 full production $0.70 soic 8 $y&z&2&t 24u08 flm rail * 1,000 piece budgetary pricing back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ufl.html (3 of 3) [26-jul-2002 2:40:26 pm]
product folder - fairchild p/n fm24c08ulz - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c08ulz 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ulz.html (1 of 3) [26-jul-2002 2:40:48 pm]
product folder - fairchild p/n fm24c08ulz - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c08ulzem8x full production $0.81 soic 8 $y&z&2&t 24u08 lze tape reel fm24c08ulzem8 full production $0.81 soic 8 $y&z&2&t 24u08 lze rail * 1,000 piece budgetary pricing back to top file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ulz.html (2 of 3) [26-jul-2002 2:40:48 pm]
product folder - fairchild p/n fm24c08ulz - 8k-bit standard 2-wire bus interface serial eeprom space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ulz.html (3 of 3) [26-jul-2002 2:40:48 pm]
product folder - fairchild p/n fm24c08ul - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c08ul 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ul.html (1 of 3) [26-jul-2002 2:41:07 pm]
product folder - fairchild p/n fm24c08ul - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c08ulm8 full production $0.66 soic 8 $y&z&2&t 24u08 lm8 rail fm24c08ulem8 full production $0.73 soic 8 $y&z&2&t 24u08 lem rail fm24c08ulmt8x full production $0.66 tssop 8 &2&t $y2408 &z2408 ul rail fm24c08ulm8x full production $0.66 soic 8 $y&z&2&t 24u08 lm8 tape reel file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ul.html (2 of 3) [26-jul-2002 2:41:07 pm]
product folder - fairchild p/n fm24c08ul - 8k-bit standard 2-wire bus interface serial eeprom fm24c08ulem8x full production $0.73 soic 8 $y&z&2&t 24u08 lem tape reel fm24c08uln full production $0.67 dip 8 $y&z&2&t 24u08 ul rail fm24c08ulmt8 full production $0.66 tssop 8 &2&t $y2408 &z2408 ul rail * 1,000 piece budgetary pricing back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08ul.html (3 of 3) [26-jul-2002 2:41:07 pm]
product folder - fairchild p/n fm24c09ufl - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c09ufl 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ufl.html (1 of 3) [26-jul-2002 2:41:28 pm]
product folder - fairchild p/n fm24c09ufl - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c09uflem8 full production $0.73 soic 8 $y&z&2&t 24u09 flem rail fm24c09uflm8x full production $0.70 soic 8 $y&z&2&t 24u09 fl tape reel fm24c09uflem8x full production $0.73 soic 8 $y&z&2&t 24u09 flem tape reel fm24c09uflm8 full production $0.70 soic 8 $y&z&2&t 24u09 fl rail * 1,000 piece budgetary pricing file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ufl.html (2 of 3) [26-jul-2002 2:41:28 pm]
product folder - fairchild p/n fm24c09ufl - 8k-bit standard 2-wire bus interface serial eeprom back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ufl.html (3 of 3) [26-jul-2002 2:41:28 pm]
product folder - fairchild p/n fm24c08u - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c08u 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08u.html (1 of 3) [26-jul-2002 2:41:50 pm]
product folder - fairchild p/n fm24c08u - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c08um8x full production $0.66 soic 8 $y&z&2&t 24u08 m8 tape reel fm24c08uvm8 full production $0.73 soic 8 $y&z&2&t 24u08 v rail fm24c08uen full production $0.71 dip 8 $y&z&2&t 24u08 en rail fm24c08uem8 full production $0.70 soic 8 $y&z&2&t 24u08 em8 rail file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08u.html (2 of 3) [26-jul-2002 2:41:50 pm]
product folder - fairchild p/n fm24c08u - 8k-bit standard 2-wire bus interface serial eeprom fm24c08um8 full production $0.66 soic 8 $y&z&2&t 24u08 m8 rail fm24c08un full production $0.67 dip 8 $y&z&2&t 24u08 n rail fm24c08uem8x full production $0.70 soic 8 $y&z&2&t 24u08 em8 tape reel * 1,000 piece budgetary pricing back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c08u.html (3 of 3) [26-jul-2002 2:41:50 pm]
product folder - fairchild p/n fm24c09ulz - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c09ulz 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ulz.html (1 of 3) [26-jul-2002 2:42:11 pm]
product folder - fairchild p/n fm24c09ulz - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c09ulzem8 full production $0.81 soic 8 $y&z&2&t 24u09 lze rail fm24c09ulzemt8 full production $0.66 tssop 8 &2&t $y2409 &z2409 lze rail fm24c09ulzem8x full production $0.81 soic 8 $y&z&2&t 24u09 lze tape reel fm24c09ulzemt8x full production $0.66 tssop 8 &2&t $y2409 &z2409 lze tape reel file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ulz.html (2 of 3) [26-jul-2002 2:42:11 pm]
product folder - fairchild p/n fm24c09ulz - 8k-bit standard 2-wire bus interface serial eeprom * 1,000 piece budgetary pricing back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ulz.html (3 of 3) [26-jul-2002 2:42:11 pm]
product folder - fairchild p/n fm24c09ul - 8k-bit standard 2-wire bus interface serial eeprom fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c09ul 8k-bit standard 2-wire bus interface serial eeprom related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description the fm24c08u/09u devices are 8192 bits of cmos non-volatile electrically erasable memory. these devices conform to all specifications in the standard iic 2-wire protocol. they are designed to minimize device pin count and simplify pc board layout requirements. the upper half (upper 4kbit) of the memory of the fm24c09u can be write protected by connecting the wp pin to v cc . this section of memory then becomes unalterable unless wp is switched to v ss . this communications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for example a microprocessor) and the slave eeprom device(s). the standard iic protocol allows for a maximum of 16k of eeprom memory which is supported by the fairchild family in 2k, 4k, 8k, and 16k devices, allowing the user to configure the memory as the application requires with any combination of eeproms. in order to implement higher eeprom memory densities on the iic bus, the extended iic protocol must be used. (refer to the fm24c32 or fm24c65 datasheets for more information.) fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ul.html (1 of 3) [26-jul-2002 2:42:36 pm]
product folder - fairchild p/n fm24c09ul - 8k-bit standard 2-wire bus interface serial eeprom back to top features l extended operating voltage 2.7v p5.5v l 400 khz clock frequency (f) at 2.7v - 5.5v l 200a active current typical m 10a standby current typical m 1a standby current typical (l) m 0.1a standby current typical (lz) l iic compatible interface m provides bi-directional data transfer protocol l sixteen byte page write mode m minimizes total write time per byte l self timed write cycle m typical write cycle time of 6ms l hardware write protect for upper half (fm24c09u only) l endurance: 1,000,000 data changes l data retention greater than 40 years l packages available: 8-pin dip, 8-pin so, and 8-pin tssop l available in three temperature ranges m commercial: 0 to +70c m extended (e): -40 to +85c m automotive (v): -40 to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c09ulem8 full production $0.70 soic 8 $y&z&2&t 24u09 le rail fm24c09uln full production $0.67 dip 8 $y&z&2&t 24u09 ln rail fm24c09ulm8x full production $0.66 soic 8 $y&z&2&t 24u09 l tape reel fm24c09ulm8 full production $0.66 soic 8 $y&z&2&t 24u09 l rail file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ul.html (2 of 3) [26-jul-2002 2:42:36 pm]
product folder - fairchild p/n fm24c09ul - 8k-bit standard 2-wire bus interface serial eeprom fm24c09ulem8x full production $0.70 soic 8 $y&z&2&t 24u09 le tape reel * 1,000 piece budgetary pricing back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c09ul.html (3 of 3) [26-jul-2002 2:42:36 pm]

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